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Disambiguation of "Taylor, Greg"

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A novel digital loop filter architecture for bang-bang ADPLL.

, , , , , , , and . SoCC, page 45-50. IEEE, (2012)

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Greg Breinholt

Greg Little

Greg Ross

Greg Kiss

Greg Foderaro

 

Other publications of authors with the same name

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor., , , , and . ISLPED, page 304-309. ACM, (2007)On-die droop detector for analog sensing of power supply noise., , and . IEEE J. Solid State Circuits, 39 (4): 651-660 (2004)A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 43 (1): 61-68 (2008)A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation., , and . IEEE J. Solid State Circuits, 54 (9): 2487-2500 (2019)Cyber Insurance Risk: Reporting Delays, Third-Party Cyber Events, and Changes in Reporting Propensity - An Analysis Using Data Breaches Published by U.S. State Attorneys General., , , and . CoRR, (2023)Information-Seeking Strategies in Medicine Queries: A Clinical Eye-Tracking Study with Gaze-Cued Retrospective Think-Aloud Protocol., and . Int. J. Hum. Comput. Interaction, 34 (6): 506-518 (2018)HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system., , , , and . CICC, page 1-4. IEEE, (2010)A Bifrost Accelerated Intermittent Small Baseline Subset Analysis Pipeline for InSAR Ground Deformation., , , and . Remote. Sens., 16 (14): 2554 (July 2024)A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS., , , , and . ISSCC, page 340-341. IEEE, (2009)Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process., , , , and . CICC, page 221-224. IEEE, (2007)