( en | de | ru )

 

Disambiguation of "Dimitroulakos, Grigoris"

Author of the publication

copydeleteadd this publication to your clipboard
From Scilab to multicore embedded systems: Algorithms and methodologies.

, , , , , , , , , , , , , , , , , , , and . ICSAMOS, page 268-275. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Grigoris Antoniou

Grigoris Psallidas

Grigoris Psallidas

 

Other publications of authors with the same name

An early memory hierarchy evaluation simulator for multimedia applications., , and . Microprocess. Microsystems, 38 (1): 31-41 (2014)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , and . IPDPS, IEEE Computer Society, (2005)Compiler-Directed Data Locality Optimization in MATLAB., , , and . SCOPES, page 6-9. ACM, (2016)MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations., , and . DASIP, page 385-386. IEEE, (2012)Resource constrained modulo scheduling for coarse-grained reconfigurable arrays., , and . ISCAS, IEEE, (2006)Mapping DSP applications on processor/coarse-grain reconfigurable array architectures., , and . ISCAS, IEEE, (2006)Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware., , and . IPDPS, IEEE, (2006)Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform., , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 352-362. Springer, (2007)Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs., , and . J. Supercomput., 35 (2): 185-199 (2006)Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays., , and . SoC, page 1-4. IEEE, (2008)