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A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)

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A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 650-654 (2017)A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)