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JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores., , and . FPGA, page 184. ACM, (2019)BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research., , , , , , , , , and 3 other author(s). ASPLOS, page 699-714. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET., , , , , , , , , and 7 other author(s). CICC, page 1-2. IEEE, (2023)Piton: A 25-core academic manycore research processor., , , , , , , , and . Hot Chips Symposium, page 1-38. IEEE, (2016)There and Back Again: A Netlist's Tale with Much Egraphin'., , , , , , , , and . CoRR, (2024)A Prediction System Service., , , and . ASPLOS (2), page 48-60. ACM, (2023)Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs., , , , , , and . ISCA, page 817-830. ACM, (2022)Cohort: Software-Oriented Acceleration for Heterogeneous SoCs., , , , and . ASPLOS (3), page 105-117. ACM, (2023)Wire sorts: a language abstraction for safe hardware composition., , , and . PLDI, page 175-189. ACM, (2021)Establishing Cooperative Computation with Hardware Embassies., , , , , , and . SEED, page 85-96. IEEE, (2022)