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Disambiguation of "Koike, Hanpei"

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A Fleng Compiler for PIE64.

, , , and . IFIP PACT, volume A-50 of IFIP Transactions, page 257-266. North-Holland, (1994)

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Ursula Koike-Good

 

Other publications of authors with the same name

A Fleng Compiler for PIE64., , , and . IFIP PACT, volume A-50 of IFIP Transactions, page 257-266. North-Holland, (1994)UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64., , and . FGCS, page 715-722. IOS Press, (1992)XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together., and . CICC, page 247-250. IEEE, (2005)Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA., , , , , , and . IEICE Trans. Inf. Syst., 90-D (12): 1947-1955 (2007)Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting., and . LP, volume 264 of Lecture Notes in Computer Science, page 159-169. Springer, (1986)The Instruction Set Architecture of the Inference Processor UNIRED II., , and . Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, volume A-23 of IFIP Transactions, page 117-128. North-Holland, (1993)Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity., , , , , , and . FPGA, page 257. ACM, (2004)High-speed low-power FinFET based domino logic., , and . ASP-DAC, page 829-834. IEEE, (2009)Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2010)Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology., , , , , , , , and . CICC, page 33-36. IEEE, (2007)