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Exploration of advanced computer technology to address analytical and noise improvement issues in machine learning.

, , , , , and . J. Syst. Softw., (November 2023)

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On Reconfiguring Memory-Centric AI Edge Devices for CIM., , , , , , , , and . ISOCC, page 262-263. IEEE, (2021)Level Selection Based 4-PAM Transmitter for Chip to Chip Communication., and . APCCAS, page 1807-1810. IEEE, (2006)On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications., , , , , , , , , and . ICCAD, page 127:1-127:8. IEEE, (2020)On Optimizing Capacitor Array Design for Advanced Node SAR ADC., , , , , , , and . SMACD, page 1-4. IEEE, (2022)Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays., , , , and . ASICON, page 1-4. IEEE, (2019)Exploration of advanced computer technology to address analytical and noise improvement issues in machine learning., , , , , and . J. Syst. Softw., (November 2023)A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO., , , , and . ISCAS, page 1-5. IEEE, (2021)A Reconfigurable In-SRAM Computing Architecture for DCNN Applications., , , , , and . VLSI-DAT, page 1-2. IEEE, (2021)An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)