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VLSI architecture of dynamically reconfigurable hardware-based cipher.

, , , и . ISCAS (4), стр. 734-737. IEEE, (2001)

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Yukio Matsudo

Yukio Yamanaka

Yukio Kamizuru

Yukio Ozawa

 

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VLSI architecture of dynamically reconfigurable hardware-based cipher., , , и . ISCAS (4), стр. 734-737. IEEE, (2001)Burst mode: a new acceleration mode for 128-bit block ciphers., , , и . CICC, стр. 151-154. IEEE, (2002)A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture., , , , , и . FPL, стр. 615-618. IEEE, (2012)Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits., , , и . ASP-DAC, стр. 361-362. IEEE, (2010)Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits., , , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 333-343 (2012)Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture., , , , , , , , , и 4 other автор(ы). IEEE Embed. Syst. Lett., 10 (4): 119-122 (2018)A dynamically reconfigurable hardware-based cipher chip., , , и . ASP-DAC, стр. 11-12. ACM, (2001)33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 502-504. IEEE, (2020)Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices., , , и . ReConFig, стр. 1-7. IEEE, (2012)Coarse-grained dynamically reconfigurable architecture with flexible reliability., , , , , , , , и . FPL, стр. 186-192. IEEE, (2009)