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Disambiguation of "Hsieh, Tong-Yu"

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On-Chip SOC Test Platform Design Based on IEEE 1500 Standard.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1134-1139 (2010)

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Yu Tong

Shelley Ching-yu Hsieh

Samuel Yu-Lung Hsieh

Tong Tong

Samuel Yu-Lung Hsieh

 

Other publications of authors with the same name

Filtering-based error-tolerability evaluation of image processing circuits., and . IOLTS, page 132-137. IEEE, (2015)A yield and reliability enhancement framework for image processing applications., , and . APCCAS, page 683-686. IEEE, (2012)On no-reference on-line error-tolerability testing for videos., , and . ETS, page 1-2. IEEE, (2018)An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications., and . ACM Trans. Design Autom. Electr. Syst., 25 (1): 3:1-3:27 (2020)Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine., , and . VLSI-DAT, page 1-4. IEEE, (2020)On Enhancing Error-Tolerability of Videos via Re-Encoding with Adaptive I-Frame Insertion., , and . ITC-Asia, page 136-141. IEEE, (2020)Test Efficiency Analysis and Improvement of SOC Test Platforms., , and . ATS, page 463-466. IEEE, (2007)A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability., and . ITC-Asia, page 52-57. IEEE, (2017)On-Chip SOC Test Platform Design Based on IEEE 1500 Standard., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1134-1139 (2010)An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (6): 930-934 (2011)