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Disambiguation of "Nakahara, Hiroki"

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A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).

, , , and . FPGA, page 290. ACM, (2017)

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Hiroki Takahashi

Hiroki Kawamura

Yasuji Nakahara

Hiroki Sumizawa

 

Other publications of authors with the same name

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (1): 73-86 (2016)Implementations of Reconfigurable Logic Arrays on FPGAs., and . FPT, page 217-223. IEEE, (2007)A packet classifier using LUT cascades based on EVMDDS (k)., , and . FPL, page 1-6. IEEE, (2013)A virus scanning engine using a parallel finite-input memory machine and MPUs., , , and . FPL, page 635-639. IEEE, (2009)Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs., , and . FCCM, page 229. IEEE, (2020)High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression., , and . FCCM, page 1-9. IEEE, (2020)An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks., and . FPL, page 298-303. IEEE, (2020)The Parallel Sieve Method for a Virus Scanning Engine., , , and . DSD, page 809-816. IEEE Computer Society, (2009)Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation., , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 371-386. Springer, (2019)Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs., , and . FPL, page 461-462. IEEE Computer Society, (2018)