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A quantitative analysis on microarchitectures of modern CPU-FPGA platforms., , , , , and . DAC, page 109:1-109:6. ACM, (2016)FPGA simulation engine for customized construction of neural microcircuits., , and . ICCAD, page 607-614. IEEE, (2013)Improved crosstalk modeling for noise constrained interconnect optimization., , and . ASP-DAC, page 373-378. ACM, (2001)A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 54 (6): 1600-1612 (2019)End-to-End Optimization of Deep Learning Applications., , and . FPGA, page 133-139. ACM, (2020)Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment., , , , and . FPGA, page 120. ACM, (2019)ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only)., , , and . FPGA, page 281. ACM, (2016)HeteroRefactor: refactoring for heterogeneous computing with FPGA., , , , , and . ICSE, page 493-505. ACM, (2020)A Comprehensive Automated Exploration Framework for Systolic Array Designs., , and . DAC, page 1-6. IEEE, (2023)Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition., , , , , , and . DAC, page 1-6. IEEE, (2023)