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Disambiguation of "Hu, Jingtong"

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Hardware/Software Co-Exploration of Neural Architectures.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4805-4815 (2020)

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Jun Hu

Zaijun Hu

Bing Hu

Hu Wang

Ruguo Hu

 

Other publications of authors with the same name

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory., , , , , and . J. Syst. Archit., 59 (7): 389-399 (2013)Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (4): 584-592 (2011)Towards Independent On-device Artificial Intelligence., and . ISVLSI, page 351. IEEE, (2022)CORUSCANT: Fast Efficient Processing-in-Racetrack Memories., , , , , and . MICRO, page 784-798. IEEE, (2022)Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory., , , , , and . FPL, page 459-462. IEEE, (2008)Developing a Miniature Energy-Harvesting-Powered Edge Device with Multi-Exit Neural Network., , , , , and . ISCAS, page 1-5. IEEE, (2021)Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment., , , , and . EUC (1), page 192-198. IEEE Computer Society, (2008)Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs., , , , and . IPDPS Workshops, page 982-989. IEEE Computer Society, (2012)Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (3): 26:1-26:20 (2020)Poster Abstract: Neural Architecture Sizing for Autonomous Systems., , , , , , , , , and 1 other author(s). ICCPS, page 289-290. IEEE, (2024)