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Disambiguation of "Mueller-Gritschneder, Daniel"

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Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface.

, , and . IEEE Embed. Syst. Lett., 12 (2): 66-69 (2020)

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Daniel Müller-Gritschneder

Daniel Mueller

Sebastian Gritschneder

Matthias Gritschneder

Max Gritschneder

 

Other publications of authors with the same name

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping., , , and . IOLTS, page 220-225. IEEE, (2018)Design and validation of fault-tolerant embedded controllers., , , , and . DATE, page 1283-1288. IEEE, (2018)The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems., , , , , , and . DATE, page 1698-1707. ACM, (2015)ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques., , , , , and . DATE, page 609-612. IEEE, (2018)The Universal Safety Format in Action: Tool Integration and Practical Application., , , , , , , and . SN Comput. Sci., 4 (2): 151 (March 2023)Cross-Layer Resilience: Challenges, Insights, and the Road Ahead., , , , , , , , , and 3 other author(s). DAC, page 198. ACM, (2019)Computation of yield-optimized Pareto fronts for analog integrated circuit specifications., and . DATE, page 1088-1093. IEEE Computer Society, (2010)Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs., , and . VLSID, page 49-54. IEEE, (2020)Effective Processor Model Generation from Instruction Set Simulator to Hardware Design., , , , , and . NorCAS, page 1-7. IEEE, (2023)Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA., , , , and . CODAI, page 6-10. ACM, (2023)