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Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture.

, , , and . ICNC, page 293-297. IEEE Computer Society, (2012)

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Low power semi-static TSPC D-FFs using split-output latch., , , and . ISOCC, page 167-170. IEEE, (2011)Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis., , , , , and . ASIAN, volume 1345 of Lecture Notes in Computer Science, page 268-282. Springer, (1997)Design and evaluation of variable stages pipeline processor chip., , , and . ASP-DAC, page 95-96. IEEE, (2011)A Mechanism for Speculative Memory Accesses Following Synchronizing Operations., , and . IPDPS, page 145-154. IEEE Computer Society, (2000)Evaluation of Variable Level Cache., , , and . ISIA, volume 86 of Communications in Computer and Information Science, page 227-233. Springer, (2010)Design and Evaluation of Variable Stages Pipeline Processor Chip., , , and . ISIA, volume 86 of Communications in Computer and Information Science, page 220-226. Springer, (2010)Dynamic Task Scheduling Scheme for a GPGPU Programming Framework., and . CANDAR, page 181-187. IEEE Computer Society, (2015)Automatic Optimization of Thread Mapping for a GPGPU Programming Framework., , , and . CANDAR, page 198-204. IEEE Computer Society, (2014)Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors., , and . Annual Simulation Symposium, page 219-226. IEEE Computer Society, (2001)Orgel: A Parallel Programming Language with Declarative Communication Streams., , , and . ISHPC, volume 1940 of Lecture Notes in Computer Science, page 344-354. Springer, (2000)