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Disambiguation of "Choi, Jaehyouk"

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A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.

, , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Andreas Choi

Chiwon Choi

Bongkyung Choi

Jinsub Choi

Carmen Choi

 

Other publications of authors with the same name

An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique., , , , and . IEEE J. Solid State Circuits, 53 (9): 2675-2685 (2018)A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration., , and . IEEE J. Solid State Circuits, 54 (6): 1564-1574 (2019)A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (7): 1960-1976 (2018)A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 635-644 (2015)A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC., , , and . ISSCC, page 396-398. IEEE, (2018)10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector., , and . ISSCC, page 194-195. IEEE, (2016)A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector., , , , and . ESSCIRC, page 210-213. IEEE, (2018)An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate., , , and . CICC, page 1-4. IEEE, (2017)Session 15 overview: RF PLLs: RF subcommittee., , and . ISSCC, page 244-245. IEEE, (2018)A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells., , and . VLSIC, page 142-. IEEE, (2015)