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Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies., , and . DAC, page 33:1-33:6. ACM, (2013)From Transistor to PLL - Analogue Design and EDA Methods., , , and . DATE, ACM, (2008)Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints., , , and . DATE, page 323-327. IEEE Computer Society / ACM, (1999)Hierarchical Characterization of Analog Integrated CMOS Circuits., , and . DATE, page 636-643. IEEE Computer Society, (1998)Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach., and . Journal of Circuits, Systems, and Computers, (2012)A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters., , , and . ICCD, page 188-193. IEEE Computer Society, (2008)Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming., , and . DATE, page 75-80. EDA Consortium, San Jose, CA, USA, (2007)Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing., , and . ICCAD, page 847-854. IEEE Computer Society / ACM, (2004)A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits., , and . ICCAD, page 557-561. IEEE Computer Society, (2000)Pareto-Front Computation and Automatic Sizing of CPPLLs., , , and . ISQED, page 481-486. IEEE Computer Society, (2007)