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A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.

, , and . ISCAS, page 2027-2030. IEEE, (1993)

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An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (12): 1522-1528 (1992)MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit., , and . ICECS, page 60-63. IEEE, (2014)A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI., , and . ISCAS, page 2027-2030. IEEE, (1993)A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI., , and . ISCAS, page 331-334. IEEE, (1994)A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit., , and . ISCAS, page 323-326. IEEE, (1994)Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique., and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 127-135. Springer, (2009)Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device., , , , and . ISIC, page 412-415. IEEE, (2014)A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition., and . Neural Networks, 5 (5): 835-841 (1992)Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect., , , and . Microelectron. Reliab., 50 (5): 607-609 (2010)A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability., and . ISCAS, page 733-736. IEEE, (2000)