Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Jayasena, Nuwan
add a person with the name Jayasena, Nuwan
 

Other publications of authors with the same name

DVFS Space Exploration in Power Constrained Processing-in-Memory Systems., , , and . ARCS, volume 10172 of Lecture Notes in Computer Science, page 221-233. Springer, (2017)Computation vs. Communication Scaling for Future Transformers on Future Hardware., , , , and . CoRR, (2023)Smart Memories: a modular reconfigurable architecture., , , , , and . ISCA, page 161-171. IEEE Computer Society, (2000)T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives., , , , and . ASPLOS (2), page 1146-1164. ACM, (2024)MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories., , , , and . HPCA, page 433-444. IEEE Computer Society, (2017)Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing., , , , and . USENIX ATC, page 281-294. USENIX Association, (2016)A comparison of core power gating strategies implemented in modern hardware., , , , , and . SIGMETRICS, page 559-560. ACM, (2014)Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 425-437. Springer, (2014)Managing DRAM Latency Divergence in Irregular GPGPU Applications., , , , and . SC, page 128-139. IEEE Computer Society, (2014)Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing., , and . MEMSYS, page 506-517. ACM, (2019)