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Disambiguation of "Bagherzadeh, Nader"

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Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system.

, , and . Comput. Electr. Eng., 35 (2): 258-285 (2009)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hassan Bagherzadeh

Nader Tawassoli

Faramarz Nader

Nader Purnaqchéband

Nader Ahmad

 

Other publications of authors with the same name

Scalable load balancing congestion-aware Network-on-Chip router architecture., , and . J. Comput. Syst. Sci., 79 (4): 421-439 (2013)Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (9): 1788-1801 (2018)Multiple Branch and Block Prediction., and . HPCA, page 94-103. IEEE Computer Society, (1997)Network Facility for a Reconfigurable Computer Architecture., , , , and . ICDCS, page 264-271. IEEE Computer Society, (1985)Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform., , , and . SoCC, page 3-6. IEEE, (2004)Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks., , , and . PDP, page 307-311. IEEE, (2020)Near-optimal message routing and broadcasting in faulty hypercubes., and . Int. J. Parallel Program., 19 (5): 405-423 (1990)Performance of symbolic applications on a parallel architecture., , , and . Int. J. Parallel Program., 16 (3): 183-214 (1987)Design of a router for network-on-chip., , and . Int. J. High Perform. Syst. Archit., 1 (2): 98-105 (2007)Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs., , , , and . IEEE Trans. Computers, 65 (3): 693-705 (2016)