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Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem.

, , and . EUROMICRO, page 21068-. IEEE Computer Society, (1998)

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Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling., , , , and . ReCoSoC, page 7-14. Univ. Montpellier II, (2007)State-of-the-Art in Rapid Prototyping., and . SBCCI, page 60-66. IEEE Computer Society, (1998)An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing., , and . SBCCI, page 341-346. IEEE Computer Society, (2000)Design of an organic electronic label on a flexible substrate for temperature sensing., , , , and . ESSCIRC, page 423-426. IEEE, (2013)Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters., , , , and . VLSI-SoC, page 302-307. IEEE, (2006)Compact image compression using simplicial and ART neural systems with mixed signal implementations., , and . ISCAS (5), page 689-692. IEEE, (2003)A low power sinusoidal clock., and . ISCAS (4), page 108-111. IEEE, (2001)A New Approach for Designing Fault-Tolerant Array Processors., and . Fault-Tolerant Computing Systems, volume 283 of Informatik-Fachberichte, page 324-331. Springer, (1991)Moment-Based Estimation of Switching Activity for Correlated Distributions., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 859-868. Springer, (2004)On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 819-828. Springer, (2004)