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An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.

A. Johnson, D. Halliday, A. Millard, A. Tyrrell, J. Timmis, J. Liu, J. Harkin, L. McDaid, and S. Karim. SSCI, page 1-8. IEEE, (2016)

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Anju Vasudevan

Nadeem Anjum

Farzana Anjum

Adeel Anjum

Maria Anjum

Other publications of authors with the same name

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.A. Johnson, S. Saha, R. Chakraborty, D. Mukhopadhyay, and S. Gören. WESS, page 1:1-1:8. ACM, (2014)Document Processing: Methods for Semantic Text Similarity Analysis.A. Qurashi, V. Holmes, and A. Johnson. INISTA, page 1-6. IEEE, (2020)Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks.A. Johnson, J. Liu, A. Millard, S. Karim, A. Tyrrell, J. Harkin, J. Timmis, L. McDaid, and D. Halliday. SSCI, page 1076-1083. IEEE, (2018)A Novel Attack on a FPGA based True Random Number Generator.A. Johnson, R. Chakraborty, and D. Mukhopadhyay. WESS, page 6. ACM, (2015)Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications.A. Johnson, S. Patranabis, R. Chakraborty, and D. Mukhopadhyay. DSD, page 431-438. IEEE Computer Society, (2016)New Avenues for Automated Railway Safety Information Processing in Enterprise Architecture: An NLP Approach.A. Qurashi, Z. Farhat, V. Holmes, and A. Johnson. IEEE Access, (2023)Dynamic Multiparty Authentication using Cryptographic Hardware for the Internet of Things.H. Al-Aqrabi, A. Johnson, and R. Hill. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, page 21-28. IEEE, (2019)LoRa-PUF: A Two-Step Security Solution for LoRaWAN.M. Aliyu, M. Hafeez, and A. Johnson. VTC2023-Spring, page 1-6. IEEE, (2023)A Multi-layer Security Model for 5G-Enabled Industrial Internet of Things.H. Al-Aqrabi, A. Johnson, R. Hill, P. Lane, and L. Liu. iSCI, volume 1122 of Communications in Computer and Information Science, page 279-292. Springer, (2019)Autonomous Learning Paradigm for Spiking Neural Networks.J. Liu, L. McDaid, J. Harkin, S. Karim, A. Johnson, D. Halliday, A. Tyrrell, J. Timmis, A. Millard, and J. Hilder. ICANN (1), volume 11727 of Lecture Notes in Computer Science, page 737-744. Springer, (2019)

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Disambiguation of "Johnson, Anju P."

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An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.

Please choose a person to relate this publication to

Anju Vasudevan

Nadeem Anjum

Farzana Anjum

Adeel Anjum

Maria Anjum

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Johnson, Anju P."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.

Please choose a person to relate this publication to

Anju Vasudevan

Nadeem Anjum

Farzana Anjum

Adeel Anjum

Maria Anjum

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.