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Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (10): 1226-1236 (1996)The crossing distribution problem IC layout., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (4): 423-433 (1995)Timing-Aware Power-Noise Reduction in Placement., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 527-541 (2007)A new reasoning scheme for efficient redundancy addition and removal., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 945-951 (2003)AFD-based method for signal line EM reliability evaluation., и . ISQED, стр. 443-449. IEEE, (2016)Minimal Delay Interconnect Design Using Alphabetic Trees., и . DAC, стр. 392-396. ACM Press, (1994)Clock network sizing via sequential linear programming with time-domain analysis., и . ISPD, стр. 182-189. ACM, (2004)Delay and Area Optimization in Standard-Cell Design., , и . DAC, стр. 349-352. IEEE Computer Society Press, (1990)Making split-fabrication more secure., и . ICCAD, стр. 91. ACM, (2016)Vertical Slit Field Effect Transistor in ultra-low power applications., , и . ISQED, стр. 384-390. IEEE, (2012)