( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
HpMC: An Energy-aware Management System of Multi-level Memory Architectures.

, , , , , , и . MEMSYS, стр. 167-178. ACM, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Claudia Roberts

Yvonne Roberts

Adam Roberts

Rolf Roberts

Richard Roberts

 

Другие публикации лиц с тем же именем

An ECL RISC microprocessor designed for two level cache., , и . Compcon, стр. 228-231. IEEE Computer Society, (1990)M-N scatter plots technique for evaluating varying-size clusters and setting the parameters of Bi-CoPaM and Uncles methods., , , и . ICASSP, стр. 6726-6730. IEEE, (2014)Splitting-while-merging framework for clustering high-dimension data with component-wise expectation conditional maximisation., , , и . ICASSP, стр. 2932-2936. IEEE, (2014)Individuum und Kollektiv: Jünger und Brecht zu Ausgang der Weimarer Republik. Orbis Litterarum, (1986)HpMC: An Energy-aware Management System of Multi-level Memory Architectures., , , , , , и . MEMSYS, стр. 167-178. ACM, (2015)System design for a low cost PA-RISC desktop workstation., , , , , , и . Compcon, стр. 208-213. IEEE Computer Society, (1991)Using non-volatile memory to save energy in servers., , и . DATE, стр. 743-748. IEEE, (2009)On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology., , и . DSD, стр. 570-578. IEEE Computer Society, (2007)On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology., , и . Microprocess. Microsystems, 32 (5-6): 244-253 (2008)Toward efficient programmer-managed two-level memory hierarchies in exascale computers., , , , , и . Co-HPC@SC, стр. 9-16. IEEE, (2014)