( en | de | ru )

 

Disambiguation of "Chi, Yuze"

Author of the publication

copydeleteadd this publication to your clipboard
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.

, , , , , , , and . FPGA, page 242-251. ACM, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Ying Chi

 

Other publications of authors with the same name

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration., , and . FPGA, page 51-57. ACM, (2020)PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs., , , , , and . FCCM, page 12-22. IEEE, (2023)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver., , , , , and . CoRR, (2022)Design Automation and Optimization for Memory-Bound Application Accelerators.. University of California, Los Angeles, USA, (2021)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency., , , , , , , and . FPGA, page 311. ACM, (2020)FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search., , , and . FPGA, page 105-110. ACM, (2016)Extending High-Level Synthesis for Task-Parallel Programs., , , , , and . FCCM, page 204-213. IEEE, (2021)StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing., , and . CICC, page 1-8. IEEE, (2022)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs., , , , , and . CoRR, (2022)TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs., , , , and . CoRR, (2023)