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Stack processor architecture and development methods suitable for dependable applications.

, , and . ReCoSoC, page 69-75. Univ. Montpellier II, (2007)

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A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delays., , , , and . CoDIT, page 294-299. IEEE, (2017)A low-cost many-to-one WSN architecture based on UWB-IR and DWPT., and . CoDIT, page 712-718. IEEE, (2014)A cost-effective parallel architecture for the CodeRAKE receiver., , , and . ICECS, page 447-450. IEEE, (2007)Implementation of a Wavelet Transform Architecture for Image Processing., , and . VLSI, volume 162 of IFIP Conference Proceedings, page 101-112. Kluwer, (1999)A Wavelet Core for Video Processing., , and . ICIP, page 395-398. IEEE, (2000)The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems., , , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 409-419. Springer, (2001)Time-shift immunity for wireless sensor network based on discrete wavelet packets., , and . Ann. des Télécommunications, 76 (1-2): 1-17 (2021)An embedded core for the 2D wavelet transform., , and . ETFA (2), page 179-186. IEEE, (2001)0-7803-7241-7.Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications., , , , , , and . DATE, page 553-558. IEEE Computer Society, (2002)Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education., , , , , and . ReCoSoC, volume 7551 of KIT Scientific Reports, page 135-139. KIT Scientific Publishing, (2010)