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Using Novel Configuration Techniques for Accelerated FPGA Aging., , , , , and . FPL, page 169-175. IEEE, (2020)Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs., , , and . IVSW, page 80-86. IEEE, (2018)Comparing fine-grained performance on the Ambric MPPA against an FPGA., , , and . FPL, page 174-179. IEEE, (2009)New approaches for in-system debug of behaviorally-synthesized FPGA circuits., and . FPL, page 1-6. IEEE, (2014)Distributed-Memory Based FPGA Debug: Design Timing Impact., and . FPT, page 350-353. IEEE, (2018)Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification., , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 483-492. Springer, (2001)A dynamic instruction set computer., and . FCCM, page 99-109. IEEE Computer Society, (1995)Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ., , and . FCCM, page 149-156. IEEE Computer Society, (2018)Source Level Debugger for the Sea Cucumber Synthesizing Compiler., , , and . FCCM, page 228-. IEEE Computer Society, (2003)Reconfigurable Computing Application Frameworks., , and . FCCM, page 251-. IEEE Computer Society, (2003)