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Disambiguation of "Manivannan, Madhavan"

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Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading.

, , , and . DAC, page 1-6. IEEE, (2020)

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Madhavan Manivannan

Soumya Madhavan

Siyamalan Manivannan

Madhavan Nallani

Dharanija Madhavan

 

Other publications of authors with the same name

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem., , , , , , , , , and 24 other author(s). CF, page 309-314. ACM, (2023)JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency., , , and . ICPP, page 828-838. ACM, (2023)Scheduling Task-parallel Applications in Dynamically Asymmetric Environments., , , , and . ICPP Workshops, page 18:1-18:10. ACM, (2020)Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints., , , and . IPDPS, page 590-601. IEEE, (2020)LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing., , , , , , , , , and 35 other author(s). CoRR, (2019)CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling., , , and . PACT, page 213-225. IEEE, (2021)SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations., , and . EuroS&P, page 631-650. IEEE, (2023)SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs., , , and . IPDPS, page 325-336. IEEE, (2024)Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading., , , and . DATE, page 967-970. IEEE, (2020)Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading., , , and . DAC, page 1-6. IEEE, (2020)