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A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.

, , , , , and . IEEE J. Solid State Circuits, 44 (7): 1942-1949 (2009)

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Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate., , , , , , and . IEEE J. Solid State Circuits, 41 (9): 2040-2051 (2006)A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS., , , , , and . IEEE J. Solid State Circuits, 44 (7): 1942-1949 (2009)A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS., , , , and . ISSCC, page 296-297. IEEE, (2010)A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS., , , , and . ESSCIRC, page 410-413. IEEE, (2008)21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS., , , , , and . ISSCC, page 366-367. IEEE, (2014)Efficient Link Architecture for On-Chip Serial links and Networks., , , , , , and . SoC, page 1-4. IEEE, (2006)A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS., , , , and . ESSCIRC, page 376-379. IEEE, (2007)A power reduction method for off-chip interconnects., , , and . ISCAS, page 265-268. IEEE, (2000)Partial reset HDR image sensor with improved fixed pattern noise performance., , , , and . IMSE, page 1-6. Society for Imaging Science and Technology, (2018)A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy., , , and . PRIME, page 21-24. IEEE, (2019)