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Disambiguation of "Zambreno, Joseph"

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Parallelizing Latent Semantic Indexing using an FPGA-based architecture.

, and . ICCD, page 432-435. IEEE Computer Society, (2016)

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Joseph Schön

Joseph Stegemann

Joseph Mitsch

Joseph Jossiphov

Joseph Müller

 

Other publications of authors with the same name

Exploring Area/Delay Tradeoffs in an AES FPGA Implementation., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 575-585. Springer, (2004)Enhancing Compiler Techniques for Memory Energy Optimizations., , and . EMSOFT, volume 2491 of Lecture Notes in Computer Science, page 364-381. Springer, (2002)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)An FPGA-based Hardware Accelerator for Iris Segmentation., , and . ReConFig, page 1-8. IEEE, (2018)Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction., , , , and . FPT, page 49-56. IEEE, (2007)Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications., , and . ICPP Workshops, page 1-8. IEEE Computer Society, (2014)Cache design for mixed criticality real-time systems., , , , , and . ICCD, page 513-516. IEEE Computer Society, (2014)Parallelizing Latent Semantic Indexing using an FPGA-based architecture., and . ICCD, page 432-435. IEEE Computer Society, (2016)An Efficient Architecture for Floating-Point Eigenvalue Decomposition., and . FCCM, page 64-67. IEEE Computer Society, (2014)Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms., , , , , and . FCCM, page 336. IEEE, (2019)