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A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS., , , , , , , , и . IEEE J. Solid State Circuits, 57 (3): 757-766 (2022)A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR., , , , и . IEEE J. Solid State Circuits, 54 (6): 1669-1681 (2019)A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , и . VLSIC, стр. 346-. IEEE, (2015)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , и . ISSCC, стр. 152-154. IEEE, (2011)A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , и . ISSCC, стр. 152-154. IEEE, (2012)Digital clock and data recovery circuit design: Challenges and tradeoffs., , и . CICC, стр. 1-8. IEEE, (2011)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , и . VLSIC, стр. 188-189. IEEE, (2012)A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR., , , , и . VLSIC, стр. 350-. IEEE, (2015)A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery., , , и . ISSCC, стр. 440-442. IEEE, (2011)A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC., , , и . ISSCC, стр. 242-244. IEEE, (2012)