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Hotspot-Aware Hybrid Memory Management for In-Memory Key-Value Stores.

, , , , and . IEEE Trans. Parallel Distributed Syst., 31 (4): 779-792 (2020)

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When FPGA-Accelerator Meets Stream Data Processing in the Edge., , , , , , and . ICDCS, page 1818-1829. IEEE, (2019)Accelerating Loop-Oriented RTL Simulation With Code Instrumentation., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4985-4998 (December 2023)Lifetime or energy: Consolidating servers with reliability control in virtualized cloud datacenters., , , , , and . CloudCom, page 18-25. IEEE Computer Society, (2012)GraphM: an efficient storage system for high throughput of concurrent graph processing., , , , , , , and . SC, page 3:1-3:14. ACM, (2019)Cache/Memory Coordinated Fair Scheduling for Hybrid Memory Systems., , , and . HP3C, page 103-111. ACM, (2020)Straggler-Aware Parallel Graph Processing in Hybrid Memory Systems., , , , and . CCGRID, page 217-226. IEEE, (2021)XenLR: Xen-based Logging for Deterministic Replay., , , and . FCST, page 149-154. IEEE Computer Society, (2008)RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network., , , , , , , , , and 2 other author(s). ACM Trans. Archit. Code Optim., 20 (4): 53:1-53:26 (December 2023)AsynGraph: Maximizing Data Parallelism for Efficient Iterative Graph Processing on GPUs., , , , , , and . ACM Trans. Archit. Code Optim., 17 (4): 29:1-29:21 (2020)MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems., , , , , and . DATE, page 1086-1091. IEEE, (2017)