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Optimal register assignment with minimum-delay compensation for latch-based design., и . APCCAS, стр. 887-890. IEEE, (2010)Mixed error correction scheme and its design optimization for soft-error tolerant datapaths., и . APCCAS, стр. 362-365. IEEE, (2016)Characterization and computation of Steiner wiring based on Elmore's delay model., и . APCCAS (2), стр. 335-340. IEEE, (2002)Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: extended abstract.. ACM Great Lakes Symposium on VLSI, стр. 91-92. ACM, (2014)A feasibility study on robust programmable delay element design based on neuron-MOS mechanism., и . ACM Great Lakes Symposium on VLSI, стр. 21-26. ACM, (2014)A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling.. ACM Great Lakes Symposium on VLSI, стр. 367-372. ACM, (2015)A Novel Framework for Procedural Construction of Parallel Prefix Adders.. ISCAS, стр. 1-5. IEEE, (2019)Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range., и . ASP-DAC, стр. 239-244. IEEE, (2012)A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices., , и . GCCE, стр. 96-99. IEEE, (2019)Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (3): 659-669 (2007)