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Disambiguation of "Mishchenko, Alan"

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Logic Optimization of Majority-Inverter Graphs.

, , , , , , and . MBMV, page 1-4. VDE Verlag, (2019)

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Oleksiy Mishchenko

Safwat Alani

Maia Alandjiyska

Yilmaz Alan

Viola Alanku

 

Other publications of authors with the same name

Combinational techniques for sequential equivalence checking., , , and . FMCAD, page 145-149. IEEE, (2010)Automated Extraction of Inductive Invariants to Aid Model Checking., , and . FMCAD, page 165-172. IEEE Computer Society, (2007)Topologically constrained logic synthesis., , and . ICCAD, page 679-686. ACM / IEEE Computer Society, (2002)Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis., , , and . ASP-DAC, page 395-402. IEEE, (2022)Practical Boolean Decomposition for Delay-driven LUT Mapping., , , and . CoRR, (2024)Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN., , , and . FCCM, page 126-132. IEEE, (2024)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Rewriting Environment for Arithmetic Circuit Verification., , , , and . LPAR, volume 57 of EPiC Series in Computing, page 656-666. EasyChair, (2018)m-Inductive Property of Sequential Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 919-930 (2016)