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mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

D. Niu, S. Li, Y. Wang, W. Han, Z. Zhang, Y. Guan, T. Guan, F. Sun, F. Xue, L. Duan, Y. Fang, H. Zheng, X. Jiang, S. Wang, F. Zuo, Y. Wang, B. Yu, Q. Ren, and Y. Xie. ISSCC, page 1-3. IEEE, (2022)

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Yijin Zhang

Xin Guan

Shaohua Guan

Kyle Guan

Jing Guan

Other publications of authors with the same name

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.Y. Guan, G. Sun, Z. Yuan, X. Li, N. Xu, S. Chen, J. Cong, and Y. Xie. IEEE Trans. Computers, 69 (7): 931-943 (2020)PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.Q. Zheng, X. Li, Y. Guan, Z. Wang, Y. Cai, Y. Chen, G. Sun, and R. Huang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5464-5475 (2022)Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.Z. Du, Y. Guan, T. Guan, D. Niu, N. Tan, X. Yu, H. Zheng, J. Meng, X. Yan, and Y. Xie. ICPADS, page 483-490. IEEE, (2022)GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.Z. Wang, Y. Guan, G. Sun, D. Niu, Y. Wang, H. Zheng, and Y. Han. ACA, volume 1256 of Communications in Computer and Information Science, page 73-86. Springer, (2020)Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.S. Li, D. Niu, Y. Wang, W. Han, Z. Zhang, T. Guan, Y. Guan, H. Liu, L. Huang, Z. Du and 4 other author(s). ISCA, page 946-961. ACM, (2022)BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices.Z. Zhou, B. Shi, Z. Zhang, Y. Guan, G. Sun, and G. Luo. DAC, page 1009-1014. IEEE, (2021)OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.Z. Du, Y. Guan, T. Guan, D. Niu, L. Huang, H. Zheng, and Y. Xie. IEEE Access, (2022)Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators.Y. Guan, N. Xu, C. Zhang, Z. Yuan, and J. Cong. APPT, volume 10561 of Lecture Notes in Computer Science, page 14-26. Springer, (2017)Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.L. Huang, Z. Zhang, S. Li, D. Niu, Y. Guan, H. Zheng, and Y. Xie. IEEE Access, (2022)FPGA-based accelerator for long short-term memory recurrent neural networks.Y. Guan, Z. Yuan, G. Sun, and J. Cong. ASP-DAC, page 629-634. IEEE, (2017)

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Disambiguation of "Guan, Yijin"

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184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

Please choose a person to relate this publication to

Yijin Zhang

Xin Guan

Shaohua Guan

Kyle Guan

Jing Guan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Guan, Yijin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

Please choose a person to relate this publication to

Yijin Zhang

Xin Guan

Shaohua Guan

Kyle Guan

Jing Guan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.