( en | de | ru )

 

Disambiguation of "Coole, James"

Author of the publication

copydeleteadd this publication to your clipboard
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing.

, , , , , , , , , and . IEEE Des. Test Comput., 28 (4): 68-77 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michael James

Audrein James

Katherine James

Mooleplackal James

Rojin James

 

Other publications of authors with the same name

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs., , , , , , , and . DAC, page 56:1-56:6. ACM, (2017)Traversal caches: a first step towards FPGA acceleration of pointer-based data structures., , and . CODES+ISSS, page 61-66. ACM, (2008)Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing., and . CODES+ISSS, page 13-22. ACM, (2010)Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation., and . IEEE Embed. Syst. Lett., 3 (3): 81-84 (2011)An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing., , , , , , , , , and . IEEE Des. Test Comput., 28 (4): 68-77 (2011)A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development., , and . HEART, page 4:1-4:6. ACM, (2018)Adjustable-Cost Overlays for Runtime Compilation., and . FCCM, page 21-24. IEEE Computer Society, (2015)Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts., and . IEEE Micro, 34 (1): 42-53 (2014)BPR: fast FPGA placement and routing using macroblocks., and . CODES+ISSS, page 275-284. ACM, (2012)Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures., and . Int. J. Reconfigurable Comput., (2010)