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Disambiguation of "Saluja, Kewal K."

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WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.

, , and . VLSI Design, page 479-484. IEEE Computer Society, (2009)

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Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Böhm

K Beheng

 

Other publications of authors with the same name

A Novel Approach for Testing Memories Using a Built-In Self Testing Technique., and . ITC, page 830-839. IEEE Computer Society, (1986)SEU tolerant SRAM cell., , , , and . ISQED, page 597-602. IEEE, (2011)An implementation and analysis of a concurrent built-in self-test technique., and . FTCS, page 164-169. IEEE Computer Society, (1988)Identifying high variability speed-limiting paths under aging., , , and . LATS, page 1-6. IEEE, (2017)Testable Design of Single-Output Sequential Machines Using Checking Experiments., and . IEEE Trans. Computers, 35 (7): 658-662 (1986)A low cost approach to calibrate on-chip thermal sensors., , , , and . ISQED, page 572-576. IEEE, (2011)Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles., , and . GLOBECOM, IEEE, (2006)Transient Fault Resilient QR Factorization on GPUs., , and . FTXS@HPDC, page 63-70. ACM, (2015)Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors., , , and . DATE, page 1572-1577. IEEE Computer Society, (2010)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits., , , , and . ASP-DAC, page 659-664. IEEE, (2006)