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Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.

G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti, and J. Jose. IoTSMS, page 227-234. IEEE, (2019)

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Maurizio Podda

Maurizio Venturini

Maurizio Zanazzi

Maurizio Serva

Maurizio Podda

Other publications of authors with the same name

Low Energy Mapping Techniques under Reliability and Bandwidth Constraints.A. Mineo, M. Masi, M. Palesi, G. Ascia, and V. Catania. HPCC/EUC, page 2088-2095. IEEE, (2013)Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti, and J. Jose. IoTSMS, page 227-234. IEEE, (2019)Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service.A. Mineo, M. Palesi, D. Patti, and V. Catania. COINS, page 1-6. IEEE, (2020)A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip.G. Ascia, V. Catania, and M. Palesi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (4): 635-645 (2005)An Instruction-Level Power Analysis Model with Data Dependency.G. Ascia, V. Catania, M. Palesi, and D. Sarta. VLSI Design, 12 (2): 245-273 (2001)Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems.A. Nuovo, M. Palesi, and V. Catania. FUZZ-IEEE, page 1-6. IEEE, (2007)Efficient design space exploration for application specific systems-on-a-chip.G. Ascia, V. Catania, A. Nuovo, M. Palesi, and D. Patti. J. Syst. Archit., 53 (10): 733-750 (2007)Bandwidth-aware routing algorithms for networks-on-chip platforms.M. Palesi, S. Kumar, and V. Catania. IET Comput. Digit. Tech., 3 (5): 413-429 (2009)Editorial: Special issue on design challenges for many-core processors.M. Daneshtalab, M. Palesi, and J. Plosila. ACM Trans. Embed. Comput. Syst., 13 (3s): 100:1-100:2 (2014)Neighbors-on-Path: A New Selection Strategy for On-Chip Networks.G. Ascia, V. Catania, M. Palesi, and D. Patti. ESTIMedia, page 79-84. IEEE Computer Society, (2006)

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Disambiguation of "Palesi, Maurizio"

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Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.

Please choose a person to relate this publication to

Maurizio Podda

Maurizio Venturini

Maurizio Zanazzi

Maurizio Serva

Maurizio Podda

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Palesi, Maurizio"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.

Please choose a person to relate this publication to

Maurizio Podda

Maurizio Venturini

Maurizio Zanazzi

Maurizio Serva

Maurizio Podda

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.