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Accurate capture of timing parameters in inductively-coupled on-chip interconnects., , , , , , and . SBCCI, page 117-122. ACM, (2004)On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study., , and . IOLTS, page 29-34. IEEE Computer Society, (2005)Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip., , , , , and . ISVLSI, page 426-427. IEEE Computer Society, (2006)Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados., , and . RITA, 11 (2): 49-74 (2004)Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices., , , and . ICECS, page 270-273. IEEE, (2017)Exploring area and total wirelength using a cell merging technique., , , and . VLSI-SoC, page 329-334. IEEE, (2019)DHyANA: A NoC-based neural network hardware architecture., , , , and . ICECS, page 177-180. IEEE, (2016)A study on layout quality of automatic generated cells., , , , and . ICECS, page 651-654. IEEE, (2010)Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation., , , , , and . SBCCI, page 196-201. ACM, (2005)Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard., , , , , and . EUSIPCO, page 560-564. IEEE, (2020)