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A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.

Z. Wan, X. Xu, W. Rhee, and Z. Wang. ICTA, page 76-77. IEEE, (2021)

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Sascha Rhee

Hanjo Rhee

Sora Rhee

Kyu Ho Rhee

Jong Il Rhee

Other publications of authors with the same name

A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications.D. Liu, X. Ni, R. Zhou, W. Rhee, and Z. Wang. IEEE J. Solid State Circuits, 52 (6): 1479-1494 (2017)A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.L. Zhang, X. Yu, Y. Sun, W. Rhee, D. Wang, Z. Wang, and H. Chen. IEEE J. Solid State Circuits, 44 (11): 2922-2934 (2009)F5: Low-power radios for sensor networks.W. Rhee, G. Burra, K. Arimoto, P. Harpe, B. Otis, and D. Ruffieux. ISSCC, page 518-519. IEEE, (2014)9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability.F. Chen, Y. Li, D. Liu, W. Rhee, J. Kim, D. Kim, and Z. Wang. ISSCC, page 162-163. IEEE, (2014)A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.Y. Zhang, X. Liu, W. Rhee, H. Jiang, and Z. Wang. ISCAS, page 1-4. IEEE, (2017)A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1+-Point Modulation.C. Ding, W. Rhee, and Z. Wang. ISCAS, page 1-4. IEEE, (2019)A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering.X. Huang, K. Zeng, W. Rhee, and Z. Wang. ISCAS, page 1-4. IEEE, (2019)A ΔΣ IR-UWB radar with sub-mm ranging capability for human body monitoring systems.W. Zhang, W. Rhee, and Z. Wang. ISCAS, page 1315-1318. IEEE, (2012)A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.X. Yu, Y. Sun, L. Zhang, W. Rhee, and Z. Wang. ISSCC, page 346-347. IEEE, (2008)A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC.W. Zhang, Y. Han, F. Chen, B. Zhou, X. Chen, W. Rhee, and Z. Wang. VLSI-DAT, page 1-4. IEEE, (2014)

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Disambiguation of "Rhee, Woogeun"

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A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.

Please choose a person to relate this publication to

Sascha Rhee

Hanjo Rhee

Sora Rhee

Kyu Ho Rhee

Jong Il Rhee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Rhee, Woogeun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.

Please choose a person to relate this publication to

Sascha Rhee

Hanjo Rhee

Sora Rhee

Kyu Ho Rhee

Jong Il Rhee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.