Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator.

A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay. ISSCC, page 404-406. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Muhammad Sanusi

Rebecca Mathew

Stanley Mathew

Mathew Joseph

Mathew Mandapathil

Other publications of authors with the same name

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS.A. Agarwal, S. Hsu, S. Mathew, M. Anders, H. Kaul, F. Sheikh, and R. Krishnamurthy. ESSCIRC, page 177-180. IEEE, (2012)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.S. Hsu, A. Agarwal, S. Realov, M. Anders, G. Chen, M. Kar, R. Kumar, H. Sumbul, P. Knag, H. Kaul and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.S. Hsu, A. Agarwal, M. Anders, H. Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, and S. Borkar. VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS.A. Agarwal, S. Hsu, M. Anders, S. Mathew, G. Chen, H. Kaul, S. Satpathy, and R. Krishnamurthy. VLSI Circuits, page 1-2. IEEE, (2016)Security keynote: Ultra-low-energy security circuit primitives for IoT platforms.S. Mathew. ITC, page 1. IEEE, (2017)8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator.M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay. ISSCC, page 142-143. IEEE, (2017)Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities.M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay. ISLPED, page 1-2. IEEE, (2017)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS.S. Vangal, M. Anders, N. Borkar, E. Seligman, V. Govindarajulu, V. Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni, J. Tschanz and 12 other author(s). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.R. Ramanarayanan, S. Mathew, F. Sheikh, S. Srinivasan, A. Agarwal, S. Hsu, H. Kaul, M. Anders, V. Erraguntla, and R. Krishnamurthy. ESSCIRC, page 210-213. IEEE, (2010)A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS.R. Kumar, A. Varna, C. Tokunaga, S. Taneja, V. De, and S. Mathew. ISSCC, page 244-245. IEEE, (2023)

BibSonomy

Disambiguation of "Mathew, Sanu"