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gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator.

, , and . ICPP, page 29:1-29:11. ACM, (2021)

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Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs., , , , , , , , , and . DATE, page 628-631. IEEE, (2022)SafeSU: an Extended Statistics Unit for Multicore Timing Interference., , , , , , , and . ETS, page 1-4. IEEE, (2021)VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations., , , , , , , , and . HPCA, page 921-934. IEEE, (2021)Evolutionary system for prediction and optimization of hardware architecture performance., , , , , , , and . IEEE Congress on Evolutionary Computation, page 1941-1948. IEEE, (2008)Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 218-229. Springer, (2014)Optimizing computation-communication overlap in asynchronous task-based programs: poster., , , , , , , and . PPoPP, page 415-416. ACM, (2019)Graph partitioning applied to DAG scheduling to reduce NUMA effects., , , , , and . PPoPP, page 419-420. ACM, (2018)POSTER: An Optimized Predication Execution for SIMD Extensions., , , , and . PACT, page 479-480. IEEE, (2019)Runtime-Guided Management of Scratchpad Memories in Multicore Architectures., , , , , , , and . PACT, page 379-391. IEEE Computer Society, (2015)Stencil codes on a vector length agnostic architecture., , , , , , , and . PACT, page 13:1-13:12. ACM, (2018)