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Synthesis of Self-Testable Controllers.

, and . EDAC-ETC-EUROASIC, page 580-585. IEEE Computer Society, (1994)

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Minimized Power Consumption for Scan-Based BIST., and . J. Electron. Test., 16 (3): 203-212 (2000)The design of random-testable sequential circuits.. FTCS, page 110-117. IEEE Computer Society, (1989)Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen, , , , and . VDI-Buch Springer Berlin Heidelberg, Berlin, Heidelberg, (2009)Efficient Online and Offline Testing of Embedded DRAMs., , , , and . IEEE Trans. Computers, 51 (7): 801-809 (2002)A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems., , , , , , and . J. Electron. Test., 30 (4): 401-413 (2014)Introduction., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 397-398 (2003)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)Testability-Enhancing Resynthesis of Reconfigurable Scan Networks., , and . ITC, page 20-29. IEEE, (2021)Test Aspects of System Health State Monitoring., , , , and . LATS, page 1-2. IEEE, (2023)Reliability Considerations forMechatronic Systems on the Basis of a State Model., , , and . ARCS Workshops, volume P-41 of LNI, page 106-112. GI, (2004)