( en | de | ru )

 

Disambiguation of "Huang, Qiuting"

Author of the publication

copydeleteadd this publication to your clipboard
A Reconfigurable DT ΔΣ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers.

, , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 525-536 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Josef Huang

Pa Huang

Zheng Huang

Yuejun Huang

Shiwei Huang

 

Other publications of authors with the same name

Multi-network Based Automatic Modulation Recognition with Confidence Fusion., , , , and . ICCT, page 1256-1260. IEEE, (2021)A wireless system with stimulation and recording capabilities for interfacing peripheral nerves in rodents., , , , , , and . EMBC, page 4439-4442. IEEE, (2016)A Reconfigurable DT ΔΣ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 525-536 (2015)Efficient channel shortening for higher order modulation: Algorithm and architecture., , , , and . ISCAS, page 2377-2380. IEEE, (2012)A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS., , and . VLSI-SoC, page 183-188. IEEE, (2010)Design and Optimization of an HSDPA Turbo Decoder ASIC., , , and . IEEE J. Solid State Circuits, 44 (1): 98-106 (2009)Efficient vlsi implementation of reduced-state sequence estimation for wireless communications., , , and . ICASSP, page 2528-2532. IEEE, (2013)Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture., , , , and . VLSI-SoC, page 279-282. IEEE, (2012)A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR., and . ISSCC, page 338-607. IEEE, (2007)A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End., , , and . ISSCC, page 260-601. IEEE, (2007)