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Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity., , and . ISCAS (5), page 453-456. IEEE, (2003)Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction., and . ISCAS (5), page 185-188. IEEE, (2004)Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design., , , and . ISCAS, IEEE, (2006)Realization of a programmable rank-order filter architecture using capacitive threshold logic gates., , and . ISCAS (1), page 435-438. IEEE, (1999)Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells., , , and . VLSI-SoC, page 234-238. IEEE, (2006)Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation., and . SoC, page 93-96. IEEE, (2003)A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering., , and . ISCAS, page 685-688. IEEE, (2000)Early wire characterization for predictable network-on-chip global interconnects., , , , , , and . SLIP, page 57-64. ACM, (2007)A compact modular architecture for high-speed binary sorting., , and . ICASSP, page 3339-3342. IEEE, (2000)