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Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM.

, , , , , , , , , , и . APCCAS, стр. 116-119. IEEE, (2012)

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Schi-chien Tsai

Ming-Cheng Tsai

Ming-chien Chang

Tun-ming Tsai

Ming-tang Tsai

 

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Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM., , , , , , , , , и 1 other автор(ы). APCCAS, стр. 116-119. IEEE, (2012)An all-digital bit transistor characterization scheme for CMOS 6T SRAM array., , , , , , , , , и . ISCAS, стр. 2485-2488. IEEE, (2012)A full-synthesizable high-precision built-in delay time measurement circuit., и . ASP-DAC, стр. 123-124. IEEE, (2009)Asymmetrical Write-assist for single-ended SRAM operation., , , , и . SoCC, стр. 101-104. IEEE, (2009)An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array., , , , , , , , , и 1 other автор(ы). VLSI-DAT, стр. 1-4. IEEE, (2012)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2012)High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability., , , и . APCCAS, стр. 614-617. IEEE, (2006)An All-Digital High-Precision Built-In Delay Time Measurement Circuit., , и . VTS, стр. 249-254. IEEE Computer Society, (2008)