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Disambiguation of "Chung, Kun Young"

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Learning-based prediction of embedded memory timing failures during initial floorplan design.

, , , , and . ASP-DAC, page 178-185. IEEE, (2016)

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Ku-Young Chung

Sae-Young Chung

Young Sup Chung

Young-Soon Chung

Young-Soon Chung

 

Other publications of authors with the same name

Industry Evaluation of Reversible Scan Chain Diagnosis., , , , , , , and . ITC, page 420-426. IEEE, (2022)Design and test of latch-based circuits to maximize performance, yield, and delay test quality., and . ITC, page 94-103. IEEE Computer Society, (2010)Learning-based prediction of embedded memory timing failures during initial floorplan design., , , , and . ASP-DAC, page 178-185. IEEE, (2016)Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing., and . ITC, page 1089-1097. IEEE Computer Society, (2003)Innovative practices session 9C DFT and data for diagnostics., and . VTS, page 1. IEEE Computer Society, (2017)Test Compression Improvement with EDT Channel Sharing in SoC Designs., , , , , , , and . NATW, page 22-31. IEEE, (2014)Comprehensive optimization of scan chain timing during late-stage IC implementation., , and . DAC, page 61:1-61:6. ACM, (2016)Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing., and . VTS, page 8-15. IEEE Computer Society, (2006)Efficient Scheduling of Path Delay Tests for Latch-Based Circuits., and . VTS, page 103-110. IEEE Computer Society, (2009)Innovative practices session 6C: Latest practices in test compression., , , and . VTS, page 1. IEEE Computer Society, (2013)