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Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)Synthesis of low-leakage PD-SOI circuits with body-biasing., , , and . ISLPED, page 287-290. ACM, (2001)Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (3): 503-514 (2021)Efficient FPGA Implementation of PCA Algorithm for Large Data using High Level Synthesis., and . PRIME, page 65-68. IEEE, (2019)Implementation analysis of NoC: a MPSoC trace-driven approach., , and . ACM Great Lakes Symposium on VLSI, page 204-209. ACM, (2006)Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS., , , , and . ISCAS, page 1-5. IEEE, (2018)A flexible UWB Transmitter for breast cancer detection imaging systems., , , and . DATE, page 1076-1081. IEEE Computer Society, (2010)Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2229-2233 (July 2024)Effects of Temperature in Deep-Submicron Global Interconnect Optimization., , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 90-100. Springer, (2003)A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization., , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 121-130. Springer, (2003)