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An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores., , , and . DAC, page 729-734. ACM, (2011)Coordinated power management of voltage islands in CMPs., , , and . SIGMETRICS, page 359-360. ACM, (2010)OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance., , , , , , , and . ASPLOS, page 395-406. ACM, (2013)Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks., , , and . HPCA, page 440-451. IEEE Computer Society, (2014)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy., and . ICLR (Poster), OpenReview.net, (2018)Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs., , , , , and . ISCA, page 69-80. ACM, (2011)MIRA: A Multi-layered On-Chip Interconnect Router Architecture., , , , , , and . ISCA, page 251-261. IEEE Computer Society, (2008)A case for dynamic frequency tuning in on-chip networks., , , , , and . MICRO, page 292-303. ACM, (2009)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)., , , , , , , , , and 1 other author(s). FPGA, page 287. ACM, (2018)A case for heterogeneous on-chip interconnects for CMPs., , and . ISCA, page 389-400. ACM, (2011)