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Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells., , , and . VLSI-SoC, page 234-238. IEEE, (2006)Low noise MCML prefix adders using 0.18 µm CMOS technology., and . Circuits, Signals, and Systems, page 467-470. IASTED/ACTA Press, (2004)Sensitivity analysis of an analog circuit model of lamprey unit pattern generator., , , and . ICNN, page 975-979. IEEE, (1997)Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design., , , and . ISCAS, IEEE, (2006)Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept., , , and . ESSCIRC, page 304-307. IEEE, (2007)Finding efficient inductor geometries in digital CMOS process for RF applications., and . Circuits, Signals, and Systems, page 558-561. IASTED/ACTA Press, (2004)Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic., and . Circuits, Signals, and Systems, page 483-487. IASTED/ACTA Press, (2004)An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations., and . ISCAS, page 1580-1583. IEEE, (1995)Estimating Node Voltages in Bipolar Circuits Using Linear Programming., and . ISCAS, page 901-903. IEEE, (1995)Analog Circuit Model of Lamprey Unit Pattern Generator., , , and . Great Lakes Symposium on VLSI, page 137-142. IEEE Computer Society, (1997)