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A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology., , and . IEEE J. Solid State Circuits, 34 (6): 748-760 (1999)MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time Sigma, Delta Modulators., , , , , , and . DATE, page 150-155. IEEE Computer Society, (2004)An ultra-low power consumption 1-V, 10-bit succesive approximation ADC., , , and . ICECS, page 634-637. IEEE, (2008)Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass Sigma-Delta modulators., , , , and . ISCAS (1), page 340-343. IEEE, (2001)High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (9): 1795-1810 (2005)Practical considerations for the design of cascade multi-bit high-frequency ΣΔ modulators., , , and . ICECS, page 161-164. IEEE, (1998)A statistical optimization-based approach for automated sizing of analog cells., , , and . ICCAD, page 594-597. IEEE Computer Society / ACM, (1994)Reconfiguration of cascade Sigma Delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers., , , , , , and . ISCAS, IEEE, (2006)Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages., , , and . DATE, page 10168-10175. IEEE Computer Society, (2003)Impact of parasitics on even symmetric split-capacitor arrays., , and . I. J. Circuit Theory and Applications, 41 (9): 972-987 (2013)