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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.

, , , , , , and . DAC, page 399-404. ACM, (2002)

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Place and Route for Secure Standard Cell Design., and . CARDIS, volume 153 of IFIP, page 143-158. Kluwer/Springer, (2004)Synthesis for real time systems: Solutions and challenges., and . VLSI Signal Processing, 9 (1-2): 67-88 (1995)Synthesis of Secure FPGA Implementations., and . IACR Cryptology ePrint Archive, (2004)Efficient Software Implementation of Ring-LWE Encryption., , , and . IACR Cryptology ePrint Archive, (2014)Secure IRIS Verification., and . ICASSP (2), page 133-136. IEEE, (2007)Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients., , , , , , and . DAC, page 399-404. ACM, (2002)A multi-bit/cell PUF using analog breakdown positions in CMOS., , , , , , , and . IRPS, page 2-1. IEEE, (2018)Revisiting Higher-Order DPA Attacks: ., , , and . CT-RSA, volume 5985 of Lecture Notes in Computer Science, page 221-234. Springer, (2010)Binary decision diagram to design balanced secure logic styles., , , and . IOLTS, page 239-244. IEEE, (2016)Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation., , , , and . CHES, volume 9293 of Lecture Notes in Computer Science, page 164-184. Springer, (2015)